1. Field of the Invention
The present invention relates to a fabrication process for a dielectric isolated complementary integrated circuit (IC), and, more particularly, to an improvement in the fabrication process for dielectric isolated regions in which the complementary transistors are fabricated.
2. Description of the Prior Art
Since the first integrated circuit, isolation between circuit elements therein has been a matter of great concern. Air isolation, dielectric isolation and junction isolation have been the main streams of element isolation development, where junction isolation has been the most successful and now is in very wide use. Dielectric isolation, which isolates circuit elements from each other using a dielectric film, such as silicon dioxide (SiO.sub.2), has been applied only in limited situations even though it provides the advantages of small stray capacitance and high breakdown voltage. The limited use has been primarily due to the difficulty of the conventional fabrication process for a dielectric isolated device, which requires not only removal of the greater part of a substrate by lapping or polishing, but also a difficult alignment of a resist pattern on a deeply grooved surface of an etched substrate to form the isolation layers. The difficulty of the process results in a decreased yield and increased costs for the IC.
Recently demand for high voltage devices has been increasing because the high voltage ICs are now used widely in electronic equipment, for example, a subscriber line interface circuit (SLIC) in an electronic telephone switching system is required to withstand several hundred volts. In this application, the IC must be a complementary IC, therefore providing both pnp and npn type transistors. For such applications, especially for fabricating complementary IC circuits, the dielectric isolation process has been recently reconsidered.
To clarify the advantages of the present invention over the prior art, a prior art process for fabricating a dielectric isolated complementary IC, as shown in FIG. 1, will be briefly described. FIG. 1 illustrates a partial cross-sectional view of the construction of an exemplary IC including dielectrically isolated complementary transistors. Such an isolation structure is sometimes called an epitaxially passivated integrated circuit (EPIC) and is a well known structure developed during the early stages of IC development (see, for example, U.S. Pat. No. 3,966,577 issued June 29, 1976, by A. K. Hochberg, entitled "Dielectrically Isolated Semiconductor Devices").
In FIG. 1, a pnp transistor is fabricated in a p-type semiconductor region P, and an npn transistor is fabricated in an n-type region N. The transistors are surrounded by a silicon dioxide layer I and a buried layer B and formed in a polysilicon (polycrystalline silicon) substrate.
First a projecting island 2 is fabricated on a p-type silicon substrate 1 as illustrated in FIG. 2. The projection is created by selective etching, where a portion of the substrate where the island 2 should be made is coated with a silicon-nitride (Si.sub.3 N.sub.4) film (not shown) and uncovered portions are etched away. It is well known that, when a silicon surface of &lt;100&gt; orientation is etched using a potassium hydroxide solution, differences in etching speed for different crystal planes result in an island-like projection 2 as in FIG. 2. This type of anisotropic etching is sometimes called a V-cut. The substrate 1 looks like FIG. 2 after the silicon nitride film covering the island 2 has been removed.
Next, as shown in FIG. 3, except for the island 2, the surface of the substrate 1 is again coated with a silicon nitride film (not shown), and boron is doped into the surface of the island 2 by ion implantation using the silicon nitride film as a mask. Then during annealing of the substrate, the doped surface of the island 2 is converted into a p-type region 3. The surface of the substrate is again heated in a wet ambient environment, and a thick silicon dioxide (SiO.sub.2) coating film 4 is grown on the surface of the island 2, as shown in FIG. 3. Finally, the silicon nitride film covering the surface of the substrate 1 is removed and the structure of FIG. 3 results. The above-discussed steps are performed using a conventional photo-lithographic process which is widely used in semiconductor fabrication. Of course there may be many modifications to the process, such as using a silicon dioxide film in the place of the silicon nitride film. The difficulties in such a dielectric isolation process are caused by the level difference between the top of the island 2 and the surface of the substrate 1. For example, the height of the island 2 projecting above the surface of the substrate 1 is approximately 40 micrometers, making mask alignment for patterning difficult, and, in addition, since it is very difficult to deposit a uniformly thick resist on a sharply slanted surface, the lack of uniformity of pattern thickness produced by such deep etching also produces problems.
An n-type semiconductor layer 5 is epitaxially grown over the substrate 1 and the projected island 2, as shown in FIG. 4. At this time, the newly grown n-type epitaxial layer 5 loses its crystalline structure in the portion over the silicon dioxide and has an amorphous structure, and becomes amorphous polycrystalline silicon (poly-silicon) resulting in island portion 2 of the substrate 1 being coated with a poly-silicon 5', while the remainder of the substrate 1 is covered with an n-type single crystal layer 5, as shown in FIG. 4.
After removing the part of the poly-silicon layer projecting above the surface of the n-type epitaxial layer 5, a similar process, as described with respect to FIGS. 2 and 3, is repeated in the n-type layer 5. That is, by using a silicon nitride film as a mask (not shown), the device is selectively etched (V-cut) leaving a new island portion 5, as shown in FIG. 5. During this process, the poly-silicon layer covering the first island 2 is also etched off. However, the silicon dioxide layer 4 is not etched by the etchant for the poly-silicon, and remains over the first island 2, even though not shown in FIG. 5. Using the silicon dioxide layer 4 as a mask, an n-type dopant, such as phosphor or arsenic, is implanted, into the surface of the substrate using a known ion implantation process, and a highly doped n.sup.+ buried layer 6 is formed by annealing. Then, the silicon dioxide layer 4 is removed by a hydrofluroic acid bath and the substrate as shown in FIG. 5 results.
Next, as shown in FIG. 6, a silicon dioxide layer 7 about 2 micrometers thick is formed over the surface of the substrate by heating the substrate in oxygen gas or by chemical vapor deposition (CVD). The silicon dioxide layer 7 covering the islands 2 and 5 is used later as the dielectric isolation layer I (see FIG. 1) isolating the semiconductor devices. Then, a poly-silicon layer is deposited over the entire surface of the substrate 1, and, finally, the substrate 1 is lapped off leaving the inverted islands 2 and 5 resulting in the substrate as shown in FIG. 1. The above explanation has been provided while emphasizing the sequence of the process relevant to the present invention. However, the process steps are all conventional and the specific details, such as etching bath temperature and time, have been omitted for the sake of simplicity.
As described above, it is necessary to form the p-type and the n-type islands in sequence, and the distance the islands project above the surface of the substrate is high. Occasionally, the height exceeds several tens of micrometers. Such level differences in the substrate surface cause difficulties in the patterning and etching of the substrate. In order to overcome the problem, conventionally, a photo-resist is applied several times to the non-planar surfaces, and the patterning and etching is also repeated several times. However, such process improvements are still inadequate and the lack of uniformity in the thickness of the photo-resist causes uneven etching. It is also necessary to provide an additional process to remove the projecting portion of the poly-silicon formed on the island 2 by grinding, etching or polishing. Such additional processes decrease the yield and increase the cost of the IC.
As described above, prior art processes do not provide a solution to overcome the etching process difficulties, and, in addition, it is necessary to repeat the process of island making (sequentially create the different conductivity islands) and to dope the surfaces of p-type and n-type islands separately. As a result, the yield of the dielectric isolated complementary IC produced in accordance with the prior art process is not good and the cost is relatively high.